1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly to a semiconductor memory device operating under a plurality of power voltages.
The present application is based on Korean Patent Application No. 96-62414 which is incorporated herein by reference for all purposes.
2. Description of the Related Art
Generally, as semiconductor memory device become more highly integrated, the thickness of the transistor gate oxide layers becomes thinner--e.g., 200 .ANG., 160 .ANG., 120 .ANG., etc.--in order to improve the performance of the transistor. However, if an external power voltage is applied directly to the thin gates of these semiconductor memory devices, the gate oxide layer may become damaged. Consequently, modern memory devices typically include an internal power voltage generating circuit which receives the external power voltage and generates a constant internal power voltage lower than the external power voltage. This internal power voltage is then applied to that portion of the semiconductor memory device as needed.
In order to apply both the external power voltage and lower internal power voltage to the memory device, respective wells of a first conductivity type (e.g. N-type) have traditionally been required for each voltage. The transistors of a second conductivity type (e.g. P-type), to which the external power voltage and internal power voltage are applied, are defined within these wells. In order to avoid the mutual interference between these transistors and wells, a region of an opposite conductivity type, such as a P-type well, is formed between the respective N-type wells to maintain a sufficient gap. Unfortunately, the advantage yielded by this design is offset by an equally important disadvantage. Though interference is reduced by the inclusion of this gap between the N-type wells, the total circuit area required for the memory chip is consequently increased.
FIG. 1 is a vertical cross-sectional view showing separated inverter circuits of the semiconductor memory device according to the prior art. As shown in FIG. 1, a first inverter 8 consists of a first P-channel transistor 3 formed within a first N-well 2 and a first N-channel transistor 7 formed within a P-well 5 or a P-type substrate 6 (referred to collectively herein as "substrate"). An external power voltage EVCC (i.e., a first power voltage) is applied to the source of the first P-channel transistor 3, and a substrate voltage Vsub is applied to the substrate.
A second inverter 13 consists of a second P-channel transistor 11 formed within a second N-well 10 and a second N-channel transistor 12 formed within the P-well 5 or the substrate 6. An internal power voltage IVCC (i.e., a second power voltage), lower than the external power voltage EVCC, is applied to the source of the second P-channel transistor 11. The substrate voltage Vsub is a ground voltage VSS or a negative voltage applied to the substrate.
An input voltage Vin(Ext) is supplied to gates 51 and 53 of the first N-channel transistor 7 and the first P-channel transistor 3, respectively. The first P-channel transistor 3 and the first N-channel transistor 7, when activated by the application of the input voltage Vin(Ext) to their gates, generate an output voltage Vout(Ext) through their common drains.
Likewise, an input voltage Vin(Int) is supplied to gates 55 and 57 of the second P-channel transistor 11 and the second N-channel transistor 12, respectively. The second P-channel transistor 11 and the second N-channel transistor 12, when activated by the application of the input voltage Vin(Int) to their gates, generate an output voltage Vout(Int) through their common drains.
In this case, the first power voltage EVCC is equal to or greater than the input voltage Vin(Ext), and the second power voltage IVCC is equal to or greater than the input voltage Vin(Int). The first and second inverters 8 and 13 are separated from each other by a constant gap to exclude mutual interference generated by the different power voltages, that is, the first and second power voltages applied respectively to the first and second N-wells 2 and 10. Consequently, the gap required between the inverter wells 2 and 10 creates an inefficiency in the layout of the memory circuit.